Field of the Invention
The present invention relates to a transient voltage suppressor, particularly to a low capacitance transient voltage suppressor.
Description of the Related Art
ESD-induced failure is a major reliability problem to all kinds of electronics, including ICs and electronic systems. ESD protection is hence required for all electronics at both IC level and system board level. The terminology of “ESD protection” is generally used for on-chip IC ESD protection. At system level, it ESD protection is typically called transient voltage suppression (TVS) protection, which generally refers to various transient surge protection according to various industrial standards, including ESD protection (IEC61000-4-2) and lightning protection (IEC61000-4-5), etc. Specifically, TVS refers to system level ESD protection component, which is also called a transient voltage suppressor. TVS components are separate transient protection parts typically placed at the input/output (I/O) interfaces of a system board to defend the system products against any incoming electrical current and voltage surges. Typically, lightning protection is considered as a different type of TVS protection because it involves much stronger transient current and voltage surges, and complies with different protection standard, i.e., IEC61000-4-5. However, while ESD protection is required for all electronics, the ESD protection components always introduce parasitic capacitance, which may affect electronic circuit performance. This is particularly true to the high-speed, high data rate interfaces, such as HDMI, DVI, USB, etc., where any ESD-induced parasitic capacitance will seriously degrade the electronic system performance. Therefore, while providing ESD protection, a good ESD protection solution ought to have minimized parasitic capacitance.
High-speed data links require robust ESD protection with parasitic capacitance lower than 0.5 Pico farad (pF), which is very challenging in designs. For example, high-datarate ports, such as HDMI, USB and DVI, on the printed circuit boards (PCB) of modern electronic products (e.g., smart phones, tablets, LCD displays, etc.) requires standalone TVS protection parts, either in discrete device or integrated circuit format. There are many prior arts offering such TVS protection solutions. FIG. 1 illustrates one such TVS protection solution consisting of diode ESD protection devices from the I/O port to the ground (GND) and power supply bus (VDD), and an ESD clamping device between VDD and GND nodes. The power clamp device can be a Zener diode 10, a silicon-controlled rectifier (SCR) or other type of active conducting structures. The GND node may be replaced by a negative power supply (VSS) as required by the PCB circuit. All ESD protection devices remain in “off” state without affecting the transient appears at I/O with respect to GND (denoted NS ESD mode), the lower ESD protection diode 12 turns on in forward mode to discharge the ESD transient. If a positive ESD transient occurs at I/O with respect to GND (denoted PS ESD mode), the upper ESD protection diode 14 in series with the Zener diode 10 will conduct the ESD pulse. When a positive ESD surge comes to I/O with respect to VDD (denoted PD ESD mode), the upper ESD protection diode 14 will be turned on to discharge the ESD surge in forward mode. If a negative ESD pulse appears to I/O with respect to VDD (denoted ND ESD mode), the lower ESD protection diode 12 and the Zener diode 10 will form a conduction path to drain the ESD pulse. Often on electronic system board, a multiple-channel TVS IC 16 may be used for ESD protection as shown in FIG. 2. The equivalent circuit for the parasitic capacitance of a TVS component is depicted in FIG. 3 where the capacitances 18, 20 and 22 are parasitic capacitances associated with the upper and lower ESD protection diodes 14 and 12 and Zener diode 10 shown in FIG. 1, respectively.
Suppose that C1, C2 and CZ respectively denote the capacitances 18, 20 and 22. Refer to the exemplar TVS component depicted in FIG. 1, one important parameter is the input parasitic capacitance (denoted as CIO) measured at the I/O with respect to GND, which has direct impact on the data rate of the electronic systems. From FIG. 3, we have CIO=C2//(C1+CZ). CIO is typically measured from I/O to GND under a positive voltage bias from 0V to VDD (e.g., 0V-5V). Under such biasing condition, C2 and CZ are mainly reverse biased PN junction capacitance that are relatively small; while C1 is forward biased, leading to a relatively larger PN junction capacitance that is also strongly affected by the bias voltage. In general, there are two major issues associated CIO for the TVS IC. First, the PN junction capacitances are relatively high even at reverse biasing because the ESD diodes are large to ensure robust ESD protection. Second, C1 of the forward-biased ESD diode 14 increases significantly as the biasing voltage increases. Both the relatively high ESD-induced capacitance and its strong relationship with the I/O bias (i.e., capacitance not flat against voltage bias) have substantial negative impact on system performance. Therefore, an ultra small and very flat (i.e., against biasing voltage) CIO is strongly preferred for modern high-speed electronics. While the TVS component illustrated in FIG. 1 is used as an example to describe this design problem, the same issue applies to all kinds of on-chip ESD protection designs at IC level and various TVS and lightning protection designs at system PCB board level.
In view of the problems and shortcomings of the prior art, the present invention provides a low capacitance transient voltage suppressor, so as to solve the afore-mentioned problems of the prior art.